Mount IP on the bus
There are many dummy modules in Wujian100, which can be customized by users. This document uses the Dummy0 module on the AHB bus to control the RGB LED peripheral by writing registers.
This experiment builds its IP in vivado, and the IP is the AXI4 interface. The control based on the three-color LED light requires 9 bits, and here the lower 9 bits of the 32-bit register 0 are used as the control output. Mount IP to wujian100, and implement and verify functions.
1. Create Block Design
Wujian100 soft core is AHB bus, VIVADO supports AXI bus IP, need to use AHB-Lite to AXI Bridge adapter module.
Click Create Block Design, enter the design name, and open the Block Design interface.
Click the plus sign to add IP, search for AHB-Lite to AXI Bridge, and double-click to add.
Click on the module, press the icon or Ctrl+T to export the port. The bridge module acts as the AXI master, and the custom IP is the AXI slave.
The port name in the source file needs to be modified later, the suffix will be removed here, it will be more convenient when editing later
Create your AXI IP core and customize your AXI IP. Click Tools->Create and Package New IP.
Select the IP to create the AXI peripheral and click Next.
You can name the IP yourself and write a description.
The bridge is the master, and we create the slave mode. As shown below, click Next.
Click the IP Catalog on the left, open the IP manager, see the myio just added → right-click myio_v1.0 → Edit in IP Packager option, click OK, then the system will automatically open another Vivado IDE to perform the user IP core.
In this module, 4 registers are set, and each register is 32 bits wide. Here, by writing data to the register, the level of the output port is controlled, thereby controlling the output of the tricolor lamp. Connect the output port to the register register.
Double click to enter myio_v1_0_S00_AXI, there is a user code area in the design file.
Increase port declarations and add user signals as needed. Here an output [31:0]myio is added to control the three-color light.
Add user logic code as required. Here, add assign myio = slv_reg0; to connect the output to register 0.
Double click to enter the top layer of IP, increase output [31:0]myio
Add .myio(myio) to the instantiation,
Changes will be refreshed. Switch to the Package IP-myio window, click the link shown in the figure, and update the top-level file that was just modified.
Repackage the IP
Now that the IP can be used, add the IP to the Block Design.
But their AXI ports are still a little different, they can't be connected, and an interconnected IP needs to be added.
Add AXI Interconnect module
Double-click to open the AXI Interconnect module, and the interfaces of Slave and Master are both 1.
You can drag and drop with the mouse to connect ports
Just click to connect automatically
Automatically connect so, click OK.
After the automatic wiring, a new module appears to connect the rst signal, delete it here and connect it manually.
Connect the reset signal manually.
Select the myio module, ctrl+t leads to the output
Change the name as before, to myio
assign address. Go to the Adress Editor interface, find myio_0, and right-click on Assign.
Modify the address to the first address of dummy0, 0x4001_0000.
Go back to the diagram window, click to verify, that there is no error, and exit block design.
2. Connect IP to wujian100
Wrapper that generates IP. Find the generated ahb_axi in Source, right-click Generate Output Products
Then right-click Create HDL Wrapper.
You can see that the wrapper is generated and can be called, or an additional layer of files can be called.
Add a top-level file to your design. Click the + sign to create a new design source file.
Create File. File name is myio_top. Click Finish.
Click OK, click Yes.
Replace main_dummy_top0 with myio_top. Instantiate ahb_axi_wrappper in myio_top and add the same port as in the original dummy module file.
Relevant RTL code:
module myio_top(haddr, hclk, hprot, hrdata, hready, hresp, hrst_b, hsel, hsize, htrans, hwdata, hwrite, hburst,//new intr, myio//new ); output [31:0] myio; input hburst; input [31:0] haddr; input hclk; input [3 :0] hprot; input hrst_b; input hsel; input [2 :0] hsize; input [1 :0] htrans; input [31:0] hwdata; input hwrite; output [31:0] hrdata; output hready; output [1 :0] hresp; output intr; wire [31:0] hrdata; wire hready; wire [1 :0] hresp; wire intr; wire [2:0] hburst; wire hready_in; assign hready_in = hready; wire [31:0] myio; ahb_axi_wrapper u_ahb_axi_wrapper(//Instantiate the ahb_axi_wrapper module .AHB_INTERFACE_haddr (haddr), .AHB_INTERFACE_hburst (hburst), .AHB_INTERFACE_hprot (hprot), .AHB_INTERFACE_hrdata (hrdata), .AHB_INTERFACE_hready_in (hready_in), .AHB_INTERFACE_hready_out (hready), .AHB_INTERFACE_hresp (hresp), .AHB_INTERFACE_hsize (hsize), .AHB_INTERFACE_htrans (htrans), .AHB_INTERFACE_hwdata (hwdata), .AHB_INTERFACE_hwrite (hwrite), .AHB_INTERFACE_sel (hsel), .myio (myio), .s_ahb_hclk (hclk), .s_ahb_hresetn (hrst_b) ); endmodule
Replace main_dummy_top0 with myio_top. Modify the instantiations in ahb_matrix_top, pdu_top, wujian100_open_top in turn.
Double-click to open the modified ahb_matrix_top file
Find the instantiation of x_main_dummy_top0
1. Also add the new output port myio, the signal needs to be led out to the top level, myio
2. Added hburst, which was not used in the previous dummy empty module, and needs to be added here.
At the beginning of the file, add output pins and definitions:
Double-click to open the modified pdu_top file:
Find the instantiated ahb_matrix_top and add myio connection
Again, add output pins and define
Double-click to open the modified wujian100_open_top file
Find the instantiated pdu_top and add the myio connection
Again, add output pins and define
The IP is now mounted.
Add the corresponding function pins in the constraint file, where the lower 9 bits of myio are connected to the 9 pins of the tricolor lamp.
As in the previous tutorial, synthesize, implement, and then generate a BIT file and download it to the development board.
3. Implementation and verification
Write simple program verification functions in CDK.